The present invention is related in general to the field of electronic systems and semiconductor devices, and more specifically to photodiodes and pixels fabricated by the CMOS technology, yet having reduced dark current, improved light sensitivity and responsivity, and high level of integration.
Digital imaging devices are becoming increasingly popular in a variety of applications such as digital cameras, fingerprint recognition, and digital scanners and copiers. Typical prior art digital imaging devices are based on Charge Coupled Device (CCD) technology. CCD devices have an array of CCD cells, each cell comprising a pixel. Each CCD pixel outputs a voltage signal proportionate to the intensity of light impinging upon the cell. This analog voltage signal can be converted to a digital signal for further processing, digital filtering, and storage. As is well known in the art, a two-dimensional digital image can be constructed from the voltage signal outputs created by a two-dimensional array of CCD cells, commonly referred to as a sensor array.
CCD arrays have the shortcoming that the CCD fabrication requires a special process flow, which is not compatible with the standard CMOS process flow dominating today""s manufacturing technology due to its flexibility and low cost. Consequently, the CCD array cannot be easily integrated with other logic circuits, such as CCD control logic and analog-to-digital converters. Additionally, in operation, a CCD array requires multiple high voltage supplies from 5 V to 12 V, and tends to consume a large amount of power.
CMOS technology has recently been considered for imager application. CMOS area (or 2-dimensional) sensor arrays can be fabricated in standard CMOS process and thus other system functions, such as controller, analog-to-digital, signal processor, and digital signal processor, can be integrated on the same chip. CMOS area array sensors (or CMOS imagers) can operate with a single low supply voltage such as 3.3 V or 5.0 V. The cost of CMOS processing is also lower than that of CCD processing. The power consumption of a CMOS sensor is lower than that of a CCD sensor.
In order to fabricate photodiodes and pixels in CMOS technology, however, a number of problems have to be overcome, foremost the unacceptably high level of reverse bias leakage or xe2x80x9cdarkxe2x80x9d current of the photodiodes. Another challenge is the best possible level of integration, the so-called xe2x80x9cfill factorxe2x80x9d. The reverse bias or dark current is dominated by generation current in the junction depletion region. This current is proportional to the depletion width and the intrinsic carrier concentration, and inverse proportional to the recombination lifetime. Methods to reduce the dark current include lowering the temperature, or operating at lower supply voltage, or reducing the recombination/generation centers in the depletion region. The latter option is the most promising.
The recombination/generation centers originate mainly from
lattice defects introduced during processing, especially
implant damage not annealed by subsequent thermal treatment;
damage induced by reactive ion etching (such as gate poly-silicon and shallow trench isolation etching);
stress-induced defects, for instance at STI edges;
surface states, prominently
electron traps at the Sixe2x80x94SiO2 interface;
depletion region extending to and including the silicon surface directly under the oxide;
impurities, for example
dopants and
metal contamination primarily from silicide.
In known technology, a number of approaches have been described to minimize at least several of these origins and thus reduce the dark current. In U.S. Pat. No. 5,625,210, issued Apr. 29, 1997 (Lee et al., xe2x80x9cActive Pixel Sensor Integrated with a Pinned Photodiodexe2x80x9d), extends the concept of a pinned photodiode, known in CCD technology, by integrating it into the image sensing element of an active pixel sensor, fabricated in CMOS technology. An additional first implant creates a photodiode by implanting a deeper n+ dopant than used by the source and drain implants, increasing the photo-response. An additional pinning layer implant, using high doses of a low energy p+ dopant, is then created near the surface; this pinning layer is not in electrical contact with the p-epitaxial layer over the p-substrate. This approach has many additional process steps and is too expensive for mass production.
Other approaches to reduce the dark current have been described at technical conferences such as ISSCC 1999, ISSCC 2000, and IEDM 2000. These approaches include optimizing the shallow trench liner oxidation in order to minimize defects at the active edge, blocking silicide, annealing with hydrogen in order to passivate defects, varying anneal cycles and well junction depths. Non of these efforts were completely satisfactory, especially with respect to minimum number of process steps and low cost manufacturing.
The challenge of cost reduction implies a drive for minimizing the number of process steps, especially a minimum number of photomask steps, and the application of standardized process conditions wherever possible. These constraints should be kept in mind when additional process steps or new process conditions are proposed to reduce photodiode dark current and improve light sensitivity and responsivity without sacrificing any desirable device characteristics. An urgent need has, therefore, arisen for a coherent, low-cost method of reducing dark current in photodiodes fabricated by CMOS technology, and, simultaneously, improve the degree of component integration at the pixel level. The device structure should further provide excellent light responsivity and sensitivity in the red as well as the blue spectrum, mechanical stability and high reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.
A highly integrated pixel, fabricated by CMOS technology, is described, comprising a photodiode formed by a n-well, with cathode, surrounded by a p-well; a reset MOS transistor formed such that its polysilicon gate is positioned across p-well and n-well regions and its source is merged with the photodiode cathode; and a sensing MOS transistor formed such that its source is combined with the drain of the reset transistor and its gate is electrically connected to the source of the reset transistor.
In the pixel of the invention, the photodiode leakage current is greatly reduced, because no n+/p-well junction is connected to the photodiode, and the fill factor is improved, because the pixel size is much reduced.
The invention applies to semiconductors both of p-type and n-type as xe2x80x9cfirstxe2x80x9d conductivity types; preferably, the semiconductors are in the 1 to 50 xcexa9com resistivity range. The semiconductor may consist of an epitaxial layer deposited on higher conductivity substrate material.
It is an aspect of the invention that the pixel is fabricated with deep sub-micron CMOS technology (such as 0.18 xcexcm and smaller), yet the large dark (leakage) current is greatly reduced, since no longer a n+/p-well junction is connected to the photodiode.
Another aspect of the invention is that the manifold integration reduces the silicon xe2x80x9creal estatexe2x80x9d consumed by the pixel; consequently, the xe2x80x9cfill factorxe2x80x9d is much improved, and the fabrication cost lowered.
Another aspect of the invention is that the concept of creating buried near-the-surface junctions and thus reducing the effect of surface-related leakage caused by traps, dangling bonds, and recombination/generation centers can be utilized.
It is an essential aspect of the present invention that the shallow compensating p-well in the n-well can be created without an additional ion implant step by using the general p-well implant. The design of the location and periphery of the remaining n-well is flexible.
Another aspect of the invention is that the compensating p-well increases the total junction depletion region of the photodiode. Consequently, more carriers are generated in the photodiode per incident light, resulting in a more sensitive photodiode.
Another aspect of the invention is that the newly created compensating p-well/n-well junction is near and about parallel to the surface. Consequently, an increased responsivity to the short wavelength spectrum is created.
Another aspect of the invention is that the n+ silicidation can be separated from the photodiode depletion region by inserting a short shallow trench isolation (STI) layer (which does not consume much real estate). This eliminates the risk of any heavy metal contamination and subsequent formation of generation-recombination centers in the depletion regionxe2x80x94a well known source of junction leakage current.
It is a technical advantage of the present invention that the dopant concentrations and the junction depths of the compensating p-well, the n-well, and/or the p-well and p-substrate can be manufactured according to pre-determined device and process modeling, and are thus very flexible.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.